The present invention relates generally to processors and more particularly to a processor with programmable virtual ports.
In current MCU (micro-control unit) GPIO (General Purpose Input/Output) and IOMUX (input/output multiplexer) design, a plurality of IO pins are usually defined into several ports with a width such as 8 bits, 16 bits or 32 bits, which can be used for function pins (e.g., sci, spi, etc.) or general IO pins, or for function verification and test purposes. Due to different system requirement, pin mux and package configuration, these addressable ports/pins are discrete in almost all MCU chips.
Discrete ports/pins have many disadvantages. For instance, it requires extra effort to configure the port program. Further, performance is degraded for data transfer when ports/pins are discrete. If the port addresses are discrete, the data programs have to be in bit mode, which decreases the application performance, and increases verification and production test time when using the ports for pattern correctness checking. In addition, if the port bus width is changed from chip to chip, the test software may not be re-usable.
Thus, it would be desirable to have a programmable non-discrete 8 bit (or 16 bit or 32 bit) width virtual port, ideally having the same width as that of a chip bus, which eliminates the above-mentioned disadvantages of discrete ports or non-available ports in low-pin-count packages.